In a phase modulator provided in an optical waveguide, or a semiconductor laser such as a direct modulation laser, it is necessary to inject an electric charge in order to change a refractive index of the optical waveguide, or cause laser oscillation. Electrically, the phase modulator and the semiconductor laser are an electric-optic conversion element including a diode with a p-n junction illustrated in FIG. 7A.
In the phase modulator, there are two methods of applying a bias voltage to the diode, i.e., applying a bias voltage in a forward direction and in a reverse direction. In consideration of an optical loss, it is preferable to employ the driving method of applying a bias voltage in the forward direction by using a pin diode structure in which it is not necessary to add impurities into the optical waveguide. In the semiconductor laser, the diode is driven by applying a bias voltage in the forward direction in order to inject an electric charge.
FIG. 7B illustrates characteristics of the electric-optic conversion element including the diode by using an equivalent circuit (see T. Usuki, “Robust Optical Data Transfer on Silicon Photonic Chip”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 30, No. 18, P. 2933, Sep. 15, 2012.). In the equivalent circuit, capacitance C and conductance (conductivity of leakage resistance) G of the diode have nonlinearity with respect to a voltage. In the case of the semiconductor laser, the equivalent circuit exhibits characteristics including an optical resonator. The capacitance C includes capacitance obtained by photons accumulated in the optical resonator, and the conductance G includes conductance obtained through a process of removing light to outside of the optical resonator. In the diode, the capacitance C and the conductance G rapidly increase at a threshold voltage VTH or more particularly at the time of driving in the forward direction.
Here, for the purpose of simplifying discussion, the capacitance C and the conductance G of the diode are assumed to have constant values CON and GON at the threshold voltage VTH or more as illustrated in FIG. 7C. In this case, an electric charge QC injected at the threshold voltage VTH or more and a leakage current monotonously increase. As illustrated in FIG. 7D, Q1, I1, and V1 respectively represent an electric charge, a leakage current, and an applied voltage exhibiting a ‘1’ state. In a ‘0’ state, the values respectively become 0. In the equivalent circuit, parasitic resistance R also exists in series with the capacitance C.
When the diode has large capacitance in a case in which the diode is driven at high speed by applying a bias voltage in the forward direction, a modulation signal has noticeable frequency dependence. Thus, a matching circuit is inserted (see T. Usuki, “Robust Optical Data Transfer on Silicon Photonic Chip”, JOURNAL OF LIGHT TECHNOLOGY< VOL. 30, No. 81, P. 2933, Sep. 15, 2012.).
FIG. 8 illustrates a circuit configuration obtained by combining a matching circuit 102 and a diode 103 with a CMOS inverter circuit 101. In the circuit configuration, capacitance of the matching circuit 102 is represented by ηCON by using efficiency η, and conductance of resistance of the matching circuit 102 is represented by ηGON. When viewed from the side of the CMOS inverter circuit 101, total capacitance is ηCON/(1+η). When the efficiency η is made sufficiently smaller than 1, the capacitance is decreased. Thus, the frequency dependence is decreased even at the time of high-speed operation.
FIG. 9A illustrates an equivalent circuit corresponding to the circuit configuration in FIG. 8. Here, an FET constituting the CMOS inverter circuit 101 is simply represented by combining internal resistance Gload and a switch SW. In the equivalent circuit, it is necessary to apply appropriate internal resistance Gload or an appropriate power supply voltage VDD in order that an optical semiconductor device outputs a ‘1’ state when the CMOS inverter circuit 101 outputs a voltage on ‘high’ side (see a load line in FIG. 9B).
FIGS. 10A, 10B, and 10C illustrate timing charts in the circuit configuration in FIG. 8 (FIG. 9A). FIG. 10A illustrates a binary signal sequence having a bit time Tbit. FIG. 10B illustrates a state of the switch SW corresponding to the signal. An electric charge injected into the diode is modulated in accordance with an output of the CMOS inverter circuit. As illustrated in FIG. 10C, a time change of the electric charge has a time constant τ. Normally, a leakage current is small, and GON<<Gload, R−1. Thus, it is found that when the efficiency η is decreased, the time constant τ is also decreased, and the high-speed operation is enabled.
In the circuit configuration in FIG. 8 (FIG. 9A), the high-speed operation is enabled by decreasing the time constant τ. However, while the electric charge is being increased from 0 to Q1, a voltage applied to the matching circuit 102 is raised, and a current flowing from the CMOS inverter circuit 101 to the diode 103 is reduced. Therefore, as illustrated in FIG. 10C, a change amount when the electric charge rises from 0 is reduced as the electric charge approaches Q1, and the electric charge is saturated. The saturation characteristics degrade an eye opening of a signal waveform.
To improve the eye opening, it is suitable to employ a pre-emphasis circuit obtained by combining two CMOS inverter circuits 111 and 112 and a delay circuit 113 (a delay time TD) without using a passive matching circuit as illustrated in FIG. 11 (see A. Kern, A. Chandrakasan, and I. Young, “18Gb/s Optical IO: VCSEL Driver and TIA in 90 nm CMOS”, P. 276, 2007 Symposium on VLSI Circuits Digest of Technical Papers.). FIG. 12A illustrates an equivalent circuit of the pre-emphasis circuit in FIG. 11. Here, the CMOS inverter circuits 111 and 112 are respectively modeled by switches SWA and SWB having internal conductance GA and internal conductance GB, respectively. Since the number of transistors in the CMOS inverter circuit 111 is larger than that in the CMOS inverter circuit 112 as illustrated in FIG. 11, GA>GB. The internal conductance GA and the internal conductance GB are designed such that a voltage V1 is applied to capacitance C by resistance-dividing a power supply voltage VDD when the switch SWA (SWB) is in an ON (OFF) state as illustrated in FIG. 12B. Moreover, an applied voltage VC of the capacitance C needs to be a threshold voltage VTH or less when the switch SWA (SWB) is in an OFF (ON) state.
FIGS. 13A, 13B, 13C, and 13D illustrate timing charts in the pre-emphasis circuit in FIG. 11 (FIG. 12A). FIG. 13A illustrates a binary signal sequence having a bit time Tbit. FIGS. 13B and 13C illustrate states of the switches SWA and SWB corresponding to the signal. Here, the state of the switch SWB is delayed by the delay time TD with respect to the state of the switch SWA. Here, TD<Tbit. For example, it is designed such that TD=Tbit/2.
As illustrated in FIG. 13D, an electric charge QC is injected into the capacitance C only during the delay time TD. Since the time constant τ itself is large, a change amount of the electric charge QC is hardly saturated during the delay time TD as compared to the case of FIG. 10C. Therefore, rising of a signal waveform is defined almost by the delay time TD, so that the eye opening is improved as compared to the case of FIG. 10C.
However, the pre-emphasis circuit in FIG. 11 (FIG. 12A) has the following problems.
First, the internal conductance of the CMOS inverter circuits 111 and 112 needs high accuracy in order to apply the voltage V1 to the capacitance C by resistance-dividing the power supply voltage VDD. Accuracy necessary for the voltage V1 is generally 100 mV or less. When the power supply voltage VDD is, for example, 2V, an error allowed in the internal conductance GA and the internal conductance GB is less than 5%. The value is too strict as accuracy demanded in the FET.
Furthermore, when an optical semiconductor device maintains a ‘1’ or ‘0’ state, a through current flows through the CMOS inverter circuits 111 and 112. Therefore, power consumption is disadvantageously increased.